1. Field of the Invention
The present invention generally relates to semiconductor devices, and in particular, the present invention relates device structures and methods which reduce junction leakage particularly in lightly doped devices. Although not limited thereto, the invention is especially applicable to low-voltage CMOS (LVCMOS), or ultra-low power CMOS (ULP), implementations, as well as to SOI (silicon-oninsulator) buried well configurations.
2. Description of the Related Art
There are a number of factors which contribute to the magnitude of a transistor device's threshold voltage. For example, to set a device's threshold voltage near zero, light doping and/or counter doping in the channel region of the device may be provided. However, due to processing variations, the exact dopant concentration in the channel region can vary slightly from device to device. Although these variations may be slight, they can shift a device's threshold voltage by a few tens or even hundreds of millivolts. Further, dimensional variations (such as channel width and especially channel length), charge trapping in the materials and interfaces, and environmental factors such as operating temperature fluctuations can shift the threshold voltage. Still further, low threshold devices may leak too much when their circuits are in a sleep or standby mode. Thus, particularly for low-threshold devices, it is desirable to provide a mechanism for tuning the threshold voltage to account for these and other variations. This can be accomplished using back biasing, i.e. controlling the potential between a device's well and source. See James B. Burr, "Stanford Ultra Low Power CMOS," Symposium Record, Hot Chips V, pp. 7.4.1-7.4.12, Stanford, Calif. 1993, which is incorporated herein by reference for all purposes.
A basic characteristic of back-biased transistors resides in the ability to electrically tune the transistor thresholds. This is achieved by reverse biasing the bulk of each MOS transistor relative to the source to adjust the threshold potentials. Typically, the potential will be controlled through isolated ohmic contacts to the source and well regions together with circuitry necessary for independently controlling the potential of these two regions.
However, in any semiconductor structure having biased and abutting n and p regions, diode leakage through the p-n junction is possible. Junction leakage is a function ofjunction bias and junction doping. The greater the junction bias, the wider the depletion region, and thus the greater the leakage. The amount of leakage also increases for lightly doped junctions which are accompanied by wide depletion regions. Conversely, leakage decreases for more heavily doped junctions having relatively narrow depletion regions. Also, while a larger depletion region is accompanied by a larger leakage, the capacitance of the junction is lower.
The problems associated with leakage current can be particularly acute for low-threshold voltage devices having intrinsic or nearly intrinsic channels. As mentioned above, such devices are characterized by the provision of as little dopant as possible to achieve high mobility in the channel region. This is accomplished by the use of near-intrinsic silicon on the substrate side of the source/drain junctions.
FIG. 1(a) illustrates an example of a back-biased n-well configuration. That is, in the exemplary CMOS configuration of FIG. 1(a), each of an NFET 101 and a PFET 102 essentially constitutes a four-terminal device. The NFET 101 is made up of an n-region source 103, a gate electrode 104, an n-region drain 105, and a p.sup.- bulk substrate 106. The NFET 101 may also include a p-well 107 as shown. Similarly, the PFET 102 includes p-region source 108, a gate electrode 109 and a p-region drain 110 formed in an n-well 111. Reference numeral 112 is a p.sup.+ plug which forms a bulk terminal or well tie for the bulk material 106, and reference numeral 113 is an n.sup.+ plug forming a well tie for the n-well 111.
In the back-biased CMOS design of FIG. 1(a), the well contact 112 of the bulk material 106 is split off from the source terminal 103 of the NFET 101 by providing a separate metallic rail contact 116 which is spaced from the metallic rail contact 114 of the source terminal 103. Rail contact 116 is connected to a bias voltage source Vpw. Likewise, the well contact 113 of the n-well 111 is split off from the source terminal 108 of the PFET 102 by providing a separate metallic rail contact 118 which is spaced from the metallic rail contact 15 of the source terminal 108. Rail contact 118 is connected to a bias voltage source Vnw. Thus, in this example, the substrate bias potential of the NFET 101 is set by Vpw, and that of the PFET 102 is set by Vnw.
FIG. 1(b) illustrates a similar design, except that the substrate or bulk of the NFET 101 is biased to Vpw by way of a metallic back plane 119, rather than by way of the well tie 116 shown in FIG. 1(a).
As mentioned above, in order to provide near-zero threshold voltages, the channel regions of the devices should be constituted of near intrinsic semiconductor material. In typical non-near-zero threshold devices, surface dopant concentrations in the channel regions will be on the order of 1e17 (per cm.sup.3), thus allowing for the selection of a base material on the order of 1e16. In the context of FIGS. 1(a) and 1(b), this would mean that the bulk material 106 would have a concentration of about 1e16 and the p-well 107 and the n-well 111 would have a concentration (particularly at the surface regions) of about 1e17. Even at these concentrations, leakage is present between the n-well 111 and the p-bulk 106. Moreover, for low threshold voltage devices, a surface dopant concentration on the order of 1e15 is desired, meaning that a bulk material is selected having a concentration of about 1e14. These reduced concentrations widen the depletion regions at the p-n junctions, and thus further exacerbate the problem of leakage currents at the p-n junctions. Such leakage is illustrated in FIGS. 1(a) and 1(b) by the multiple arrows extending across the boundary between the n-well 111 and the p-bulk 106.
Junction leakage can present problems in other configurations as well. For example, FIG. 2 is a simplified view of an SOI buried well device. This particular device is characterized by a buried n-well 202 (i.e., an inverse well) implanted beneath a buried oxide layer 204. The buried well 202 is an n+ region forming a back gate electrode. The oxide layer 204 is buried in a p-substrate material 206 which is lightly doped to accommodate the concentration characteristics needed for the channel region located above the oxide layer 204 and between source and drain regions 208 and 210. Reference number 207 is an isolation oxide. As an example, the n-well may have a concentration of about 1e17, and the p-substrate 206 may have a concentration on the order of 1e16. As illustrated by the multiple arrows in FIG. 2, the device suffers junction leakage between the n-well 202 and the p-substrate 206.